Small adaptions to the control unit and datapath of a RISC-V processor enable us to apply forward-mode automatic differentiation in hardware to arithmetic instructions. The presented processor design extends an existing implementation of the RISC-V ISA, written for high-level synthesis in C. With some adaptions to the existing architecture, we enable automatic differentiation in hardware. To that extent, we introduce custom RISC-V instructions. The synthesized design runs on an FPGA.

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Referenten: Johannes Schoder, Institute for Computer Science, University of Jena

Zeit: 16:00 Uhr

Ort: Hybrid (Room 32-349 and via Zoom)